Rolf Drechsler

Rolf Drechsler

drechsler@uni-bremen.de
Institution: University of Bremen / DFKI
Department: Institute of Computer Science
Position: Head of the Computer Architecture Group (Uni Bremen), Director Cyber-Physical Systems Group Director (DFKI)
http://www.rolfdrechsler.de/

Circuits and System Descriptions, Algorithms and Data Structures, Verification, Test Pattern Generation, New Technologies

  • A Comparison of Repositioning and Scheduling Algorithms for the Ride-Hailing Problem (2027)

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    Published at: Lecture Notes in Computer Science (Volume: 16830 LNCS)
    DOI: 10.1007/978-3-032-32335-4_24

  • Synthesis for testability and verifiability: Polynomial formal verification and test pattern generation for KFDD circuits (2026)

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    Published at: Microprocessors and Microsystems (Volume: 124)
    DOI: 10.1016/j.micpro.2026.105320

  • Advances in Instruction Compression and Memory Footprint Reduction for RISC-V (2026)

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    Published at: Proceedings of the 23rd ACM International Conference on Computing Frontiers 2026 Workshops and Special Sessions Cf 2026 Companion
    DOI: 10.1145/3801488.3807976

  • Simulation-Based Hardware Exploration for Shapley Value Calculations (2026)

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    Published at: Studies in Health Technology and Informatics (Volume: 338)
    DOI: 10.3233/SHTI260899

  • An HDL-centric synthesis and verification approach for RRAM-based neuromorphic systems (2026)

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    Published at: Microprocessors and Microsystems (Volume: 122)
    DOI: 10.1016/j.micpro.2026.105278

  • Device-to-logic variability propagation in RRAM-based logic-in-memory architectures (2026)

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    Published at: Neuromorphic Computing and Engineering (Volume: 6)
    DOI: 10.1088/2634-4386/ae65d5

  • Polynomial Debugging and Fault Correction of Combinational Circuits With Constant Cutwidth (2026)

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    Published at: IEEE Transactions on Circuits and Systems I Regular Papers (Volume: 73)
    DOI: 10.1109/TCSI.2025.3633991

  • Linear Formal Verification of Sequential Circuits using Weighted-AIGs (2026)

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    Published at: ACM Transactions on Design Automation of Electronic Systems (Volume: 31)
    DOI: 10.1145/3799714

  • Formally Verifying Multiply-and-Accumulate Architectures Using Symbolic Computer Algebra (2026)

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    Published at: SN Computer Science (Volume: 7)
    DOI: 10.1007/s42979-026-04859-z

  • LLM-based Generation of High-Level Benchmarks for MVL Designs (2026)

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    Published at: Proceedings of the International Symposium on Multiple Valued Logic
    DOI: 10.1109/ISMVL68998.2026.00040